Various synchronous serial protocols exist in which clock and data are transmitted on separate lines. One of the most common implementations of a synchronous serial interface is the serial peripheral interface (SPI) bus which comprises separate data lines for input and output, a clock line, optionally a select line and/or a slave select line.
The I2S bus uses a similar number of lines, but provides for a different transmission protocol. Microcontrollers often implement the SPI protocol to be enhanced so that the SPI interface can emulate an I2S interface. The I2S protocol uses a bit clock signal BCLK on the clock line and a separate word clock line. The word clock is often referred to as a left/right clock signal LRCLK. Generally, with each edge of the LRCLK a left or right channel data word is serially transmitted using the bit clock signal. The I2S protocol is optimized for audio data. Depending on the configuration, the audio data word having 16, 24, or 32 bits is transferred between devices. In particular, the 24 bit mode is often emulated by using 32 bits or requires some data processing to be implemented correctly.
There exists a need for an improved implementation of an I2S interface, in particular in a microcontroller.